1. Technical Field
Embodiments of the present invention generally relate to computers. More particularly, embodiments relate to retrieving data blocks in computer processing architectures.
2. Discussion
In the computer industry, the demand for higher processing speeds is well documented. While such a trend is highly desirable to computers, it presents a number of challenges to industry participants. A particular area of concern is data retrieval.
Modern day computer processors are organized into one or more “pipelines,” where a pipeline is a sequence of functional units (or “stages”) that processes instructions in several steps. Each functional unit takes inputs and produces outputs, which are stored in an output buffer associated with the stage. One stage's output buffer is typically the next stage's input buffer. Such an arrangement allows all of the stages to work in parallel and therefore yields greater throughput than if each instruction had to pass through the entire pipeline before the next instruction could enter the pipeline. In order to maximize the speed at which instructions are fed into the pipelines, data blocks including the instructions are organized into prediction arrays and various levels of cache, such as trace cache, instruction cache, etc. The prediction and cache architectures can be accessed relatively quickly and help reduce the need to access slower, off-chip memory.
When a full linear address of a data block is encountered, the data block is retrieved from a respective data array if the full linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. If the data array is a prediction data array, the data block includes a branch prediction address having a size that equals the size of the full linear address. If the data array is a cache array, the data block includes, inter alia, a stored linear address having a size that equals the size of the full linear address. In either case, the tag array is indexed based on the full linear address, and therefore must be sized accordingly. As a result, fewer entries are available for the same sized data array, or a larger data array is required for the same number of entries. Since more entries are known to enhance performance, a difficult tradeoff must often be made between size and performance. There is therefore a need for an approach to processing addresses that enables the use of smaller tag arrays and therefore larger data arrays within a fixed area budget (number of bits).